module counter4 (
    input clock,
    input reset,
    input en,
    output [3:0] out
);

reg [3:0] counter;
wire [3:0] c_in;

assign out = counter;
adder4 count(.a(counter), .b(4'b0), .cin(1'b1), .s(c_in), .count());
always@(posedge clock) begin
    counter <= reset ? 4'b0 : en ? c_in : counter;
    // counter <= reset ? 4'b0 : en ? (counter+1'b1) : counter;
    
end
    
endmodule